1. Field of the Invention
The present invention relates to a delay time calculation apparatus for calculating the delay time of a gate after a process variation and to an integrated circuit design apparatus using the same.
2. Description of Related Art
A semiconductor integrated circuit is composed of a plurality of gates. A delay time of each gate (called “gate_delay” from now on) is defined as a sum of a delay time occurring within the gate (called “cell_delay” from now on) and a delay time (called “wire_delay” from now on) occurring in wire connected to the gate.
FIG. 10 is a schematic diagram illustrating a gate delay gate_delay(typ) in a typical condition, in which the delay time is typical (see, expression (1)); FIG. 11 is a schematic diagram illustrating a gate delay gate_delay(max) in a maximum condition, in which the cell delay is maximum (see, expression (2)); and FIG. 12 is a schematic diagram illustrating a gate delay gate_delay(min) in a minimum condition, in which the cell delay is minimum (see, expression (3)).gate_delay(typ)=cell_delay(typ)+wire_delay(typ)  (1) gate_delay(max)=cell_delay(max)+wire_delay(max)  (2)gate_delay(min)=cell_delay(min)+wire_delay(min)  (3)
Next, a calculation method of the cell_delay and wire_delay constituting the gate_delay will be described.
FIG. 13 is a schematic diagram illustrating a delay calculation model of the gate_delay(typ) in the typical condition. In FIG. 13, the reference numeral 1 designates a delay calculation model of the cell_delay(typ) in the typical condition, and 2 designates a delay calculation model of the wire_delay(typ) in the typical condition.
The reference symbol VDD(typ) designates a power supply voltage in the typical condition; Rs(typ) designates a source resistance of the cell in the typical condition, Cd(typ) designates a diffusion capacitance of the cell in the typical condition; R(typ) designates a wiring resistance in the typical condition; and C(typ) designates a wiring capacitance in the typical condition.
First, when an automatic placement and routing apparatus of an integrated circuit design apparatus places a plurality of gates of a semiconductor integrated circuit and lays out routing among a plurality of gates, a conventional delay time calculation apparatus captures the results of the placement and routing to identify the delay calculation model of the gate_delay(typ) as illustrated in FIG. 13.
Subsequently, the conventional delay time calculation apparatus selects a target cell for the delay time calculation from among a plurality of cells, and determines the source resistance Rs(typ) and diffusion capacitance Cd(typ) of the cell in the typical condition, referring to the results of the placement and routing. Likewise, it determines the wiring resistance R(typ) and wiring capacitance C(typ) of the wiring connected to the cell in the typical condition.
Determining the source resistance Rs(typ), diffusion capacitance Cd(typ), wiring resistance R(typ) and wiring capacitance C(typ), the conventional delay time calculation apparatus calculates the cell_delay(typ) and wire_delay(typ) by substituting them into the following functions Fcell( ) and FWire().cell_delay(typ)=Fcell(Rs(typ), Cd(typ), C(typ), R(typ))  (4)wire_delay(typ)=FWire(Rs(typ), Cd(typ), C(typ), R(typ))  (5)
Calculating the cell_delay(typ) and wire_delay(typ), the conventional delay time calculation apparatus adds them to calculate the gate_delay(typ).gate_delay(typ)=cell_delay(typ)+wire_delay(typ)  (6)
So far, the calculation of the gate delay time in the typical condition, the gate_delay(typ), is described before the process variation (before the process in which transistor characteristics or wiring geometry varies, for example). The calculation of the gate delay time after the process variation will be described below.
As the factors of the process variation, there are transistor characteristic variation and wiring geometry variation.
The transistor characteristic variation corresponds to the variations in the source resistance Rs(typ) and diffusion capacitance Cd(typ) of FIG. 13. As for these variations, the following expressions hold.Rs(max)>Rs(typ)>Rs(min)  (7)Cd(max)>Cd(typ)>Cd(min)  (8)where Rs(max) and Cd(max) are the source resistance and diffusion capacitance in the maximum condition, and Rs(min) and the Cd(min) are the source resistance and diffusion capacitance in the minimum condition.
On the other hand, the wiring geometry variation corresponds to the variations in the wiring capacitance C(typ) and wiring resistance R(typ) of FIG. 13.
FIG. 16 shows an example of the wiring geometry in a typical condition. The example includes a target wire 11 at the center. Surrounding the target wire 11, there are an upper wire 12 at the top, a lower wire 13 at the bottom, and adjacent wires 14 and 15 on both sides. The distance between the target wire 11 and upper wire 12 is TU, and the distance between the target wire 11 and lower wire 13 is TL. The wire width of the target wire 11 is L, the wiring spacing between the target wire 11 and adjacent wires 14 and 15 is S, and the wiring pitch is L+S.
In this case, the wiring resistance and wiring capacitance of the target wire 11 are R(typ) and C(typ), respectively.
FIG. 17 shows an example of a wiring geometry in a maximum condition. In the example, the distance between the target wire 11 and upper wire 12 is (TU−tu), and the distance between the target wire 11 and lower wire 13 is (TL−t1). The wire width of the target wire 11 is L+1, and the wiring spacing between the target wire 11 and adjacent wires 14 and 15 is (S−½). In this case, the wiring resistance and wiring capacitance of the target wire 11 are R(max) and C(max), respectively.
Compared with the wiring geometry in the typical condition of FIG. 16, the wiring geometry of FIG. 17 has the distance to the upper wire 12 reduced by tu, the distance to the lower wire 13 reduced by t1, the wire width increased by 1, and the wiring spacing reduced by ½. The wiring pitch, however, maintains its value L+S.
FIG. 18 shows an example of a wiring geometry in a minimum condition. In the example, the distance between the target wire 11 and upper wire 12 is (TU+tu), and the distance between the target wire 11 and lower wire 13 is (TL+t1). The wire width of the target wire 11 is L−1, and the wiring spacing between the target wire 11 and adjacent wires 14 and 15 is (S+½). In this case, the wiring resistance and wiring capacitance of the target wire 11 are R(min) and C(min), respectively.
Compared with the wiring geometry in the typical condition of FIG. 16, the wiring geometry of FIG. 18 has the distance to the upper wire 12 increased by tu, the distance to the lower wire 13 increased by t1, the wire width reduced by 1, and the wiring spacing increased by ½. The wiring pitch, however, maintains its value L+S.
The wiring resistance and the wiring capacitance have the following relationships.
 R(max)<R(typ)<R(min)  (9)C(max)>C(typ)>C(min)  (10)
As described above, the process variation consists of the transistor characteristic variation and wiring geometry variation. However, the conventional delay time calculation apparatus calculates the gate delay time after the process variation without using the actual values after the process variation. In other words, it uses none of the source resistances Rs(max) and Rs(min), diffusion capacitances Cd(max) and Cd(min), wiring resistances R(max) and R(min), and wiring capacitances C(max) and C(min) in the maximum and minimum conditions. Instead, it calculates the gate delay time using process variation coefficients KPcell(max) and KPcell(min) for the cell delay, and process variation coefficients KPWire(max) and KPWire(min) for the wire delay.
More specifically, as for the cell_delay(max) and cell_delay(min) in the maximum and minimum conditions, the conventional delay time calculation apparatus calculates them by multiplying the cell_delay(typ) in the typical condition by the process variation coefficients KPcell(max) and KPcell(min) for the cell delay, respectively.
Here, the process variation coefficients KPcell(max) and KPcell(min) for the cell delay are coefficients common to all the cells of the semiconductor integrated circuit rather than proper coefficients belonging to only the target cell for the delay time calculation.                                                                         cell_delay                ⁢                                  (                  max                  )                                            =                            ⁢                              cell_delay                ⁢                                  (                  typ                  )                                ×                                  KPcell                  ⁡                                      (                    max                    )                                                                                                                          =                            ⁢                                                Fcell                  ⁡                                      (                                                                  Rs                        ⁡                                                  (                          typ                          )                                                                    ,                                              Cd                        ⁡                                                  (                          typ                          )                                                                    ,                                              C                        ⁡                                                  (                          typ                          )                                                                    ,                                              R                        ⁡                                                  (                          typ                          )                                                                                      )                                                  ×                                                                                                      ⁢                              KPcell                ⁡                                  (                  max                  )                                                                                        (        11        )                                                                                    cell_delay                ⁢                                  (                  min                  )                                            =                            ⁢                              cell_delay                ⁢                                  (                  typ                  )                                ×                                  KPcell                  ⁡                                      (                    min                    )                                                                                                                                        ⁢                                                Fcell                  ⁡                                      (                                                                  Rs                        ⁡                                                  (                          typ                          )                                                                    ,                                              Cd                        ⁡                                                  (                          typ                          )                                                                    ,                                              C                        ⁡                                                  (                          typ                          )                                                                    ,                                              R                        ⁡                                                  (                          typ                          )                                                                                      )                                                  ×                                                                                                      ⁢                              KPcell                ⁡                                  (                  min                  )                                                                                        (        12        )            
Likewise, as for the wire_delay(max) and wire_delay(min) in the maximum and minimum conditions, the conventional delay time calculation apparatus calculates them by multiplying the wire_delay(typ) in the typical condition by the process variation coefficients KPWire(max) and KPWire(min), respectively.
The process variation coefficients KPWire(max) and KPWire(min) for the wire delay, however, are values determined by considering only variations in the wiring resistance R(typ) and wiring capacitance C(typ) under the assumption that all the cells of the semiconductor integrated circuit have the same source resistance Rs(typ) and diffusion capacitance Cd(typ).                                                                         wire_delay                ⁢                                  (                  max                  )                                            =                            ⁢                              wire_delay                ⁢                                  (                  typ                  )                                ×                                  KPWire                  ⁡                                      (                    max                    )                                                                                                                          =                            ⁢                                                FWire                  ⁡                                      (                                                                  Rs                        ⁡                                                  (                          typ                          )                                                                    ,                                              Cd                        ⁡                                                  (                          typ                          )                                                                    ,                                              C                        ⁡                                                  (                          typ                          )                                                                    ,                                              R                        ⁡                                                  (                          typ                          )                                                                                      )                                                  ×                                                                                                      ⁢                              KPWire                ⁡                                  (                  max                  )                                                                                        (        13        )                                                                                    wire_delay                ⁢                                  (                  min                  )                                            =                            ⁢                              wire_delay                ⁢                                  (                  typ                  )                                ×                                  KPWire                  ⁡                                      (                    min                    )                                                                                                                          =                            ⁢                                                FWire                  ⁡                                      (                                                                  Rs                        ⁡                                                  (                          typ                          )                                                                    ,                                              Cd                        ⁡                                                  (                          typ                          )                                                                    ,                                              C                        ⁡                                                  (                          typ                          )                                                                    ,                                              R                        ⁡                                                  (                          typ                          )                                                                                      )                                                  ×                                                                                                      ⁢                              KPWire                ⁡                                  (                  min                  )                                                                                        (        14        )            
Calculating the cell_delay(max) and cell_delay(min) and the wire_delay(max) and wire_delay(min) after the process variation as described above, the conventional delay time calculation apparatus calculates the gate_delay(max) and gate_delay(min) after the process variation by adding the cell delay and wire delay after the process variation (see, FIGS. 14 and 15).gate_delay(max)=cell_delay(max)+wire_delay(max)  (15)gate_delay(min)=cell_delay(min)+wire_delay(min)  (16)
The conventional delay time calculation apparatus with the foregoing configuration has the following problem. Although it can calculate the delay time of the gate accurately when the process variation coefficients KPcell(max) and KPcell(min) for the cell delay and the process variation coefficients KPWire(max) and KPWire(min) for the wiring match the target gate of the delay time calculation, it cannot calculate the delay time of the gate when the errors of the process variation coefficients increase.
In particular, as for the process variation coefficients KPWire(max) and KPWire(min) for the wiring, they are determined considering only the variations in the wiring resistance R(typ) and wiring capacitance C(typ) under the assumption that the source resistance Rs(typ) and diffusion capacitance Cd(typ) are the same to all the cells of the semiconductor integrated circuit. Accordingly, when the source resistance of the cell Rs(typ) and diffusion capacitance Cd(typ), to which the wires are connected, differ from the foregoing values, the errors of the process variation coefficients KPWire(max) and KPWire(min) for the wiring increase.